1. Field of the Invention
The present invention relates to a carrier for mounting a semiconductor chip and, in particular, a type of lead attachment for allowing the circuit to approach the limitations of the semiconductor chip rather than being limited by the semiconductor package and its attached leads.
2. Description of the Prior Art
Present methods of mounting high frequency transistor chips and the like for use as amplifier limiters, microwave transistors, mixer and limiter diodes, computer switching devices, microwave amplifiers for x-band applications, and FETS, may be said to fall into three general groups comprising a direct mounted chip, flip chip, and packaged transistor. In each case, the chip is bonded to a desired location either on a transistor package or in a circuit. Then wires are attached to the chip for emitter and base connections. These wires are then connected to another point which may be a circuit element or leads emanating from the transistor package.
In the past, it has been recognized that one problem of high frequency transistor assemblies is a lead inductance of the emitter. To help solve this problem, transistor manufacturers have made wide ribbon leads from the transistor package to outside circuits. The wires that connect the transistor chip to these ribbon leads, however, has received little attention from the aspect of introducing unwanted inductance.
For example, for a wire which is short compared to a wavelength, the wire inductance can be computed by the equation L = ZA/C, where L is the inductance, A is the wire length, Z is the characteristic impedance of the system, and C is the velocity of light in the medium. For a typical transistor, A = 0.024 inches and Z = 300 ohms to provide an inductance L = 0.5 nanohenrys. For an application in a microwave transistor, a typical frequency is 7 GHz. At this frequency, the inductive reactance of each emitter lead is 25 ohms to provide a total emitter impedance of 12.5 ohms because each emitter lead is connected in parallel. The effect of this feedback impedance can be evaluated by assuming intrinsic chip transistor to be capable of 6 db of gain at 7 GHz. This corresponds to a voltage gain of 2 if the source and load impedances are equal.
A method of computing the result of emitter feedback may be provided by the formula GV = G/[G(K/L)+1], where GV is the resultant voltage gain, G is the intrinsic voltage gain, K is the emitter impedance, and L is the load impedance. If the load impedance L = 50 ohms, then the resultant voltage gain will be 1.33, which is a power gain of 2.5 db, that is, the wire leads from the transistor chip to the package leads cause a 3.5 db decrease in maximum available gain. Such a decrease in gain results in the transistor package and attached leads being as important as the limitations of the transistor chip.